1. Field of the Invention
The present invention relates to a method for performing a built-in and at-speed test in a system-on-chip, and more particularly, a method for implementing a built-in and at-speed self-test including tests of critical paths in the system-on-chip.
2. Description of the Prior Art
Integrated circuits have been developed greatly, so the density of an integrated circuit has become higher. A system-on-chip, or SOC, integrating a complicated system into an independent chip, is superior to a system-on-PCB in weight, volume, performance, price, etc. However, a generative duration of a circuit test is proportional to the cube of a scale of the circuit. If a designer of a SOC ignores test issues of the SOC before completing the design, the cost of testing the SOC may be beyond the cost of manufacturing the SOC in mass production. Therefore, test issues are challenges in the development of SOCs.
Generally, a chip test is run by controlling and observing signals in circuits of a chip to determine whether the chip works well or not. In order to run a controllable and observable test, one of the DFT (design for testability) technologies in common use is used as a scan method. The scan method connects memory units in the chip, such as flip-flops, latches, etc., into a scan chain, so contents in the memory units are accessed through shifts in the scan chain. When performing a test, test patterns are shifted into the scan chain, and test results are shifted out from the scan chain. The test patterns are a set of logic values, and errors, if any, will be detected when the test results are different from ideal values. Traditionally, the chip test uses a single stuck-at fault (SSF) model, which models a defective circuit node as a stuck-at-one fault or a stuck-at-zero fault, meaning that signals in the node are locked in logic 0 (SA0) or logic 1 (SA1). Furthermore, tests for chips of deep sub-micron procedures must include various real-time or at-speed fault models, such as a transition fault model, a path delay fault model, etc.
The transition fault model includes a slow-to-rise model and a slow-to-fall model. Take the slow-to-rise model shown in FIG. 1 for example. An observing window is an acceptable delay time of a transition. If an expected output of a node cannot be captured in the observing window when performing a test, the node is considered to have a transition fault.
The path delay fault model is similar to the transition fault model except that the path delay fault model tests a total delay of a path in a chip. Please refer to FIG. 2, which illustrates a schematic diagram of a path delay fault model. In the path delay fault model, each test is aimed at a timing path in circuits. The test launches events or give values into an input of the timing path, and gathers or captures expected outputs from an output of the time path during an observing window.
In the prior art, the transition fault model can be generated by a scan chain, but a fault coverage of the transition fault model does not include tests of critical paths. The fault coverage means a ratio of detected faults to all possible faults, while the critical paths means paths having a delay duration greater than an expected duration. Therefore, to complete the tests of critical paths, the prior art must consume extra resources.